Just a thought - I haven't investigated this at all...

The m68k jit.h (and possibly other CPU arches as well) mentions that there
is no standard for flushing caches, which is necessary for proper JIT.
Instead, a GCC hack is used.

I propose another way: mprotect.

It appears, at least for NetBSD/hp300, that if you change page permissions
from PROT_READ|PROT_WRITE to PROT_READ|PROT_EXEC, then both instruction
and data caches will be flushed.  Yes, you need to flush both.

This will require substantial changes to the JIT, since you must ensure that
trampoline areas as well as pages of JIT code are PROT_READ|PROT_WRITE when
you want to write to them, and PROT_READ|PROT_EXEC when you want to exec
them.  Also, other threads must be locked out of executing code on these
pages while you are writing to them, for obvious reasons.